1. Field of the Invention
This invention pertains to the field of integrated circuit technology, and more particularly to methods for dielectrically isolating regions of semiconductor bodies in which integrated circuit devices are formed.
2. Background Information
The current state-of-the-art process technology for forming deep trenches to achieve device isolation typically employs a dielectric mask in connection with the step of etching the silicon trenches in which the isolating dielectric material is to be deposited. This is typically accomplished by a reactive ion etch (RIE) technique. For example, the masking dielectric, typically SiO.sub.2, is deposited by a chemical vapor deposition process by means of a barrel reactor or low pressure chemical vapor deposition (CVD) furnace system. This trench-defining masking oxide layer is patterned using conventional lithography and is etched anisotropically, preferably using CF.sub.4. Following the etching of the masking oxide layer--and, in the usual case, several underlying field dielectric layers composed of SiO.sub.2 and Si.sub.3 N.sub.4 --the photoresist overlying the whole structure is stripped and the reactive ion etching of the silicon trenches is executed.
In order to provide further detail of prior art processes which are directed to achieving deep trench etching for isolation purposes, reference may be made to U.S. Pat. No. 4,318,751 and to U.S. Pat. No. 4,104,086, both of which are assigned to the assignee of the present invention.
The first of the above cited patents provides in its introduction an extensive citation of references and a summary of the various approaches that have been taken in the recent past to achieving the desired isolation among devices formed in an integrated monolithic structure. In particular, this patent outlines the problem associated with a previously known dielectric isolation scheme referred to as recessed oxide isolation (ROI), which has the unfortunate result of preventing the device junction sidewalls from fully butting against the dielectric isolation, and thus imposes the need for wider tolerance on device lateral dimensions. That patent also notes that the very recently developed technique of deep dielectric isolation (DDI) avoids such problem, particularly in that the side walls of the DDI structure can be made nearly vertical--at least in principle.
The second patent recited above, that is, U.S. Pat. No. 4,104,086, likewise gives an extensive review of the prior art techniques in isolating devices. It points out that dielectric isolation in trenches, as contrasted with P-N junction isolation and the like, has the substantial advantage that it allows the butting of the circuit elements against the isolation walls and thereby results in greater density of packing of the active and passive devices on the integrated circuit chip.
It will be appreciated that the methods described in U.S. Pat. No. 4,104,086 are directed to providing grooves or trenches of sufficient taper such that the deposited SiO.sub.2 will not contain any openings or provide a poor quality dielectric region in the center of the filled groove or trench. Furthermore, that patent provides a method directed to ameliorating the so-called N+ underetching problem. For example, it is often found that the very highly doped silicon of the subcollector layer is etched more isotropically under certain conditions of reactive ion etching than regions of lower doping. Accordingly, U.S. Pat. No. 4,104,086 provides a technique which includes the use of a reactive chlorine specie ambient having defined pressures and etch rates.
Whatever the merits, advantages and features of the aforenoted two patents, there still remain several difficulties or problems associated with the formation of trenches for dielectric isolation. Thus, relatively thick masking oxide layers are required because the conventional etch rate ratios (ERR) of silicon with respect to a silicon oxide mask over the usable operating conditions of the various species of gas used for etching is generally less than 10 to 1. Moreover, image resolution of the desired minimum trench widths (.ltoreq.2.5 .mu.m) becomes difficult when photoresist layers .gtoreq.1.5 .mu.m are required to mask the reactive ion etching (by CF.sub.4) of the combined thickness of the masking layer of SiO.sub.2 and the field dielectric layers (approximately 0.8-1.0 .mu.m).
As a further consequence of the conventional ways of etching the deep trenches, it turns out that the slope of the field dielectric layers at the top of the trenches generally replicates the slope of the photoresist sidewalls (approximately 55.degree.-75.degree.), which results in significant variation in etch bias during the trench etch procedure. Moreover, the variable etch bias negatively impacts parameter control for butted emitters and resistors (width). The aforenoted oxide slope at the top of the trench also results in P to P leakage of butted PNP lateral transistors when slopes .ltoreq.75.degree. are formed.
It should also be noted that the photo limited yield of trench mask levels is typically poor, this being due primarily to particulate contamination in the relatively thick masking SiO.sub.2 layer formed by chemical vapor deposition (CVD). For example, this yield is produced because the masking layers are typically about 0.5 to 1.0 .mu.m thick.
It must also be pointed out that it has been known in principle to provide preferential or selective etching of the silicon body vis-a-vis the overlying dielectric layers, including a masking layer of SiO.sub.2 and the like. Reference may be made, for example, to U.S. Pat. No. 4,330,384; and to articles by Schaible and Schwartz in IBM Technical Disclosure Bulletins Vol. 21, No. 7 of Dec. 1978 and Vol. 22, No. 5 of Oct. 1979. U.S. Pat. No. 4,330,384 describes a plasma etching technique directed to etching a silicon body wherein the etching gas contains at least SF.sub.6. However, there is no teaching in this patent with respect to which of the many techniques for providing a dielectric layer of SiO.sub.2 is utilized. On the other hand, the disclosures of the two IBM Technical Disclosure Bulletins cited above are special cases which are concerned with the use of chlorine concentrations in the reactive ion etching of silicon, and are directed to obtaining fairly high concentrations of Cl.sub.2 of the order of 20% without causing lateral etching in the sub-collector region.
Whatever the features, advantages, and benefits of the various references cited above, none of them enables solving the multiple problems encountered in the technology of trench etching in achieving effective isolation of devices.
Accordingly, it is a primary object of the present invention to enable a reduction in device size of approximately 40% in fabricating a monolithic integrated circuit structure.
It is an ancillary object of the present invention to solve the image resolution problem in connection with deep trench isolation; that is, to enable image resolution of minimum trench widths of the order of 2.5 .mu.m.
A related object is to avoid the undesirable slope normally obtained in the field dielectric layers at the top of the trenches, thereby avoiding significant variations in etch bias or process bias during the trench etching operation.
An additional object is to improve the photo limited yield (PLY) of trench mask levels by avoiding the normally occurring particulate contamination in the relatively thick SiO.sub.2 layers.
Another object, in connection with the initial or preparatory etching operations that are conducted prior to actual formation of the trenches, is to provide such a significantly higher etch rate ratio that substantially vertical walls can be realized in the field dielectric and the overlying masking layer of SiO.sub.2 ; that is to say, the trench defining masking layer which overlies the field dielectric layers, the latter remaining as part of the finished structure.
A further object is to obtain an extremely high selectivity in etching at the stage when the trenches are to be formed in the silicon body. It has been known before to employ etching techniques which include SF.sub.6 or Cl.sub.2. However, these techniques have been used in connection with SiO.sub.2 masking layers which have been deposited by chemical vapor deposition, and inherently such layers do not permit the high etch rate ratios desired.
Yet another object is to minimize attack of the field dielectric layers during stripping of the residual mask layer of SiO.sub.2, such stripping involving the use of a dilute HF solution.